1. Technical Field
The present disclosure generally relates to validation and verification testing and more specifically to a method and system for coverage measure testing at an architectural level of integrated circuitry.
2. Description of the Related Art
Microprocessors are being built with complex architectures comprising a number of functional units. The state space of the processor architecture is very large, given the range of input values and architecture states in various execution units, such as Floating Point (FP) Units, vector units, and integer units and given the interaction between various units and the combination of events of various units. This huge state space necessitates extensive testing, while ensuring maximal coverage in minimal time. The coverage statistics are complex and are not apparent from the test case. Determining appropriate coverage in test case generators presents a lot of redundancy and creates enormous overhead in execution time.